1. Field of the Invention
This invention relates to magnetic memory arrays and, more particularly, to magnetic memory array configurations.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
Magnetic random access memory (MRAM) devices are non-volatile semiconductor devices which operate through the use of magnetic fields. Typically, an MRAM device includes a plurality of conductive lines with which to generate magnetic fields. The conductive lines may be spaced perpendicular to each other within a plane such that an array of overlap points exists between the lines. An MRAM device may further include a magnetic cell junctions interposed between the conductive lines at such overlap points. In general, the magnetic cell junctions may be adapted to store data information for the device. As such, data may be written to or read from the magnetic cell junctions. In some cases, the conductive lines may be referred to as “bit” and “digit” lines. In general, “bit” lines may refer to conductive lines arranged in contact with magnetic cell junctions that are used for both write and read operations of the magnetic junctions. “Digit” lines, on the other hand, may refer to conductive lines spaced adjacent to the magnetic cell junctions that are used primarily during write operations of the magnetic cell junctions.
During a write operation, current may be applied to a bit line and a digit line corresponding to a particular magnetic junction to create a magnetic field with which to set the magnetic direction of the magnetic cell junction. The set magnetic direction may represent either a “1” or a “0” for the stored data bit. During a read operation, however, magnetic fields are not used to gather the stored information from a magnetic cell junction. Rather, data may be read from a magnetic cell junction by creating a current path from a corresponding bit line through the magnetic cell junction to an underlying transistor such that a resistance measurement may be obtained. The underlying transistor may be turned “on” by the application of voltage along another conductive line of the MRAM device. In some embodiments, the conductive line may be referred to as a “word” line. In general, a word line may include a plurality of transistors respectively coupled to magnetic junctions aligned along a row or column of the array. As such, an MRAM device may also include a plurality of word lines. In addition, an MRAM device may include other lines and structures with which to operate the memory array. For example, an MRAM device may include interconnect lines, isolation regions, contact structures, and ground lines.
Unfortunately, as MRAM device dimensions and spacings therebetween decrease, room for such a plurality of lines and structures becomes increasingly difficult. As such, the presence of such a plurality of lines and structures becomes a limiting factor in the size of a memory array. In addition, the time needed to induce the voltage pulse used to activate the transistors along the word line gradually increases along the line. Such a time delay may be referred as the resistance and capacitance (RC) time constant of a line. In particular, the resistance and, therefore, the capacitance of a conductive line increases along a length of the line, increasing the time needed to induce the voltage pulse used to select the transistors from one end of the line to another. Consequently, as the number of memory cells within an array increases, the amount of time needed to operate all of the devices may need to be longer. Such a reduction in time naturally reduces the operating speed of the array. In some cases, an MRAM array may fail to function properly if too much time is needed to select the transistors.
Furthermore, as the desire for smaller transistors and memory cells continues, the width of transistors continues to decrease. In addition, conventional arrays typically require isolation structures with relatively large widths between memory cells such that adequate isolation may be provided. Such relatively large widths of the isolation structures restrict the width of the transistors. In general, as transistor width decreases, the parasitic resistance of the transistor increases. Consequently, the differential resistance measured during a read operation of an array having transistors with relatively small widths may be lower than an array having transistors with relatively large widths. Such a relatively reduction in differential resistance may inherently reduce the reliability of the device.
In general, a memory cell may include one or more magnetic cell junctions and the circuitry used to read and write from the junctions. As such, in addition to the magnetic cell junctions, a memory cell may include electrodes, underlying transistors, and any contact structures used to electrically connect the components. In addition, a memory cell may further include portions of the bit and digit lines used at the intersection of the magnetic cell junctions. Typically, the logic state of a memory cell may be determined (i.e., read) by comparing it to a cell with a different logic state. As such, in some cases, memory cells may include a pair of magnetic junctions such that a differential signal may be measured between the junctions. Such a configuration may be referred to as a “differential memory cell array.” In yet other embodiments, a memory cell may include a single magnetic junction and may be compared to a dummy memory cell which is used for comparing the logic states of all of the memory cells arranged along a particular row or column of the array. Such a configuration may be referred to as a “single memory cell array.”
Variations in the transistors of the memory cells, however, may cause disturbances in the measured signals, diminishing the differential resistance between the memory cells. Although the transistors are generally formed from the same fabrication process, they may differ slightly in their construction and/or functional characteristics. For example, transistors formed from the same fabrication process may differ slightly in diffusion depth due to dopant inconsistencies within the semiconductor substrate. In addition or alternatively, transistors may differ slightly in width due to lithographic inconsistencies. Furthermore, variations in capacitance and resistance within the transistors may differ slightly due to variations in threshold voltage, channel length, and/or channel width. In some embodiments, such variations may be caused by misalignment of the layers within the transistor. In any case, variations within the transistors may lead to parasitic resistances, which may diminish the differential signal between the memory cells. As a result, the parasitic resistance of a transistor may make the state of the corresponding programmed memory cell more difficult to determine.
Therefore, it would be advantageous to develop an MRAM array which generates a relatively small amount of parasitic resistance during a read operation of the array. In particular, it would beneficial to develop an MRAM array with lower transistor parasitic resistance than a conventional MRAM array. In addition, it would be advantageous to fabricate an MRAM array with a word line having a lower RC time constant than those of conventional arrays. Moreover, it would be advantageous to produce an MRAM array with transistors having larger widths than conventional arrays without increasing the size of the memory cells within the array.